As integrated circuits (ICs), especially application-specific ICs (ASICs), have become increasingly complex, testing their functionality to ensure that they operate properly has become increasingly challenging. IC testing involves two general categories: functional testing and structural testing. Functional testing involves stimulating the primary inputs of the IC and measuring the results at the primary outputs of the integrated circuit. Functional testing exercises the functionality of logic elements within the IC and is a time-honored method of testing that the IC can perform its intended operations. However, creating a robust functional test for a complex IC is very labor intensive, and attendant test equipment can be uneconomical.
To economize effort and cost involved in IC testing, structural testing has emerged as an alternative to functional testing. In a structural test, the internal storage elements of the IC are used to control and observe the IC internal logic. This is generally done by linking the storage elements into a serial shift register or “scan chain” when a test mode signal is applied. This technique is commonly referred to as “scan testing.” Generally, an IC having scan testing capability includes a number of scan chains, each comprising a number of interconnected multiplexers and registers connected to the functional logic of the integrated circuit. The registers in a scan chain are typically implemented using D flip-flops. A scan chain can be many hundreds of thousands of flip-flops in length, and is generally divided into a smaller number of shorter scan chains, each typically comprising on the order of one hundred to one thousand flip-flops and multiplexers.
During scan testing, scan data that is provided to the IC at an input/output (I/O) pad is serially clocked into, i.e., loaded into, the scan chain registers. After the scan data is loaded, a primary input state is applied to the combinational logic of the integrated circuit. The combination of the scanned-in present state and the applied primary inputs comprises the test stimulus. The values of the primary outputs are then measured and a single clock cycle is executed to capture the response of the circuit to the stimulus. To complete the scan test, the values captured in the registers are then serially scanned out of the scan chain to an I/O pad. Scan chains can be scanned out serially, i.e., one after another. Alternatively, multiple scan chains can be scanned out in parallel. Parallel scan can be much faster than serial scan if a sufficient number of I/O pads are used.
Another type of testing is known as boundary scan. Boundary scan is a method for testing interconnects between devices on printed circuit boards or between sub-blocks inside an IC. Boundary scan testing has been standardized by the Joint Test Action Group (JTAG) as IEEE Std. 1149.1. For purposes of board-level testing, a JTAG-enabled IC includes dedicated “test cells” connected to each I/O pad of the IC that can selectively override the functionality of that pad when instructed to enter a JTAG test mode. These cells can be programmed via the JTAG scan chain to drive a signal onto a pad and across an individual trace on a circuit board. The cell at the destination of the board trace can be programmed to read the value at the pad, verifying that the board trace properly connects the two pads. In the case of performing boundary scan testing between IC sub-blocks, test cells disposed between the sub-blocks allow the sub-blocks to be controlled in the same manner as if they were physically independent circuits.
Increasing IC complexity has strained I/O pad resources. That is, a more complex IC of the same physical dimensions as a less complex IC will generally have no more I/O pads available to transfer data to and from it than the less complex IC. I/O pads are used not only to transmit and receive functional data, i.e., data that relates to the IC's primary function (for example, a microprocessor function), but also parallel-scan test data. While in some ICs the same I/O pad serves to transfer both functional data in the IC's normal operational mode and parallel-scan data in a test mode, it would still be desirable to maximize the I/O available for parallel-scan testing. In general, the less I/O that is available for parallel-scan testing, the larger the test vector depth and longer the wafer and package tests.
In part to alleviate the strain on standard I/O pad resources, ICs have incorporated increasing numbers of Serializer/De-serializers or “SerDes.” (The term “standard I/O pad” is used herein to refer to an I/O pad that is not a SerDes I/O pad.) A SerDes is logic that converts data that exists inside the IC in parallel form into a serial bit stream for output from the chip, and converts a serial bit stream input to the chip into parallel form for use inside the IC. A high-speed SerDes I/O pad can provide higher bandwidth data transfer than a standard I/O pad. For this reason, SerDes is becoming the dominant technique for transferring data into and out of ICs. (The term “SerDes” is commonly used to refer both to the logic itself as well as the technique or method by which it operates.)
The data signals for which a SerDes has been used for inter-chip transfer include not only functional data, but also JTAG data. That is, a SerDes transmitter (i.e., the serializer portion) can have as its inputs both a functional data signal and a JTAG data signal, and include a multiplexer that selects whether the SerDes is to output (out of the IC) the serialized functional data or, alternatively, the JTAG data on its associated SerDes I/O pad. Likewise, a SerDes receiver (i.e., the de-serializer portion) can have as its outputs both a functional data signal and a JTAG data signal, and include selection circuitry that selects whether the SerDes is to output (to other circuitry in the IC) the parallelized functional data or, alternatively, the JTAG data.
Some SerDes use differential, rather than single-ended, I/O pads. One pair of SerDes I/O pads transmits “true” and “complement” output signals, and another pair of SerDes I/O pads receives true and complement input signals. The IEEE Std. 1149.6 extends the 1149.1 (JTAG) boundary scan testing standard to allow testing of differential-mode circuitry via such I/O pads.